View AD698_1945707.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a universal lvdt signal conditioner AD698 ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features single chip solution, contains internal oscillator and voltage reference no adjustments required interfaces to half-bridge, 4-wire lvdt dc output proportional to position 20 hz to 20 khz frequency range unipolar or bipolar output will also decode ac bridge signals outstanding performance linearity: 0.05% output voltage: 6 11 v gain drift: 20 ppm/ 8 c (typ) offset drift: 5 ppm/ 8 c (typ) product description the AD698 is a complete, monolithic linear variable differen- tial transformer (lvdt) signal conditioning subsystem. it is used in conjunction with lvdts to convert transducer mechan- ical position to a unipolar or bipolar dc voltage with a high de- gree of accuracy and repeatability. all circuit functions are included on the chip. with the addition of a few external passive components to set frequency and gain, the AD698 converts the raw lvdt output to a scaled dc signal. the device will operate with half-bridge lvdts, lvdts connected in the series op- posed configuration (4-wire), and rvdts. the AD698 contains a low distortion sine wave oscillator to drive the lvdt primary. two synchronous demodulation channels of the AD698 are used to detect primary and second- ary amplitude. the part divides the output of the secondary by the amplitude of the primary and multiplies by a scale factor. this eliminates scale factor errors due to drift in the amplitude of the primary drive, improving temperature performance and stability. the AD698 uses a unique ratiometric architecture to eliminate several of the disadvantages associated with traditional ap- proaches to lvdt interfacing. the benefits of this new cir- cuit are: no adjustments are necessary; temperature stability is improved; and transducer interchangeability is improved. the AD698 is available in two performance grades: grade temperature range package AD698ap C40 c to +85 c 28-pin plcc AD698sq C55 c to +125 c 24-pin cerdip product highlights 1. the AD698 offers a single chip solution to lvdt signal conditioning problems. all active circuits are on the mono- lithic chip with only passive components required to com- plete the conversion from mechanical position to dc voltage. 2. the AD698 can be used with many different types of posi- tion sensors. the circuit is optimized for use with any lvdt, including half-bridge and series opposed, (4 wire) configurations. the AD698 accommodates a wide range of input and output voltages and frequencies. 3. the 20 hz to 20 khz excitation frequency is determined by a single external capacitor. the AD698 provides up to 24 volts rms to differentially drive the lvdt primary, and the AD698 meets its specifications with input levels as low as 100 millivolts rms. 4. changes in oscillator amplitude with temperature will not af- fect overall circuit performance. the AD698 computes the ratio of the secondary voltage to the primary voltage to deter- mine position and direction. no adjustments are required. 5. multiple lvdts can be driven by a single AD698 either in series or parallel as long as power dissipation limits are not exceeded. the excitation output is thermally protected. 6. the AD698 may be used as a loop integrator in the design of simple electromechanical servo loops. 7. the sum of the transducer secondary voltages do not need to be constant. functional block diagram a b amp oscillator voltage reference a b filter amp AD698
AD698Cspecifications rev. b C2C (@ t a = +25 8 c, v cm = 0 v, and v+, vC = 6 15 v dc, unless otherwise noted) AD698sq AD698ap parameter min typ max min typ max unit transfer function 1 v out = a b 500 m a r 2 v overall error t min to t max 0.4 1.65 0.4 1.65 % of fs signal output characteristics output voltage range 6 11 6 11 v output current, t min to t max 11 11 ma short circuit current 20 20 ma nonlinearity 2 t min to t max 75 6 500 75 6 500 ppm of fs gain error 3 0.1 6 1.0 0.1 6 1.0 % of fs gain drift 20 6 100 20 6 100 ppm/ c of fs output offset 0.02 6 1 0.02 6 1 % of fs offset drift 5 6 25 5 6 25 ppm/ c of fs excitation voltage rejection 4 100 100 ppm/db power supply rejection ( 12 v to 18 v) psrr gain 50 300 50 300 ppm/v psrr offset 15 100 15 100 ppm/v common-mode rejection ( 3 v) cmrr gain 25 100 25 100 ppm/v cmrr offset 2 100 2 100 ppm/v output ripple 5 4 4 mv rms excitation output characteristics (@ 2.5 khz) excitation voltage range 2.1 24 2.1 24 v rms excitation voltage (resistors are 1% absolute values) (r1 = open) 6 1.2 2.15 1.2 2.15 v rms (r1 = 12.7 k w ) 2.6 4.35 2.6 4.35 v rms (r1 = 487 w ) 14 21.2 14 21.2 v rms excitation voltage tc 7 100 100 ppm/ c output current 30 50 30 50 ma rms t min to t max 40 40 ma rms short circuit current 60 60 ma dc offset voltage (differential, r1 = 12.7 k w ) t min to t max 30 6 100 30 6 100 mv frequency 20 20 k 20 20 k hz frequency tc 200 200 ppm/ c total harmonic distortion C50 C50 db signal input characteristics a/b ratio usable full-scale range 0.1 0.9 0.l 0.9 signal voltage b channel 0.1 3.5 0.1 3.5 v rms signal voltage a channel 0.0 3.5 0.0 3.5 v rms input impedance 200 200 k w input bias current (bin, ain) 1 5 1 5 m a signal reference bias current 2 10 2 10 m a excitation frequency 0 20 k 0 20 k hz power supply requirements operating range 13 36 13 36 v dual supply operation ( 10 v output) 13 13 v single supply operation 0 v to +10 v output 17.5 17.5 v 0 v to 10 v output 17.5 17.5 v current (no load at signal and excitation outputs) 12 15 12 15 ma t min to t max 18 18 ma operating temperature range C55 +125 C40 +85 c
AD698 rev. b C3C notes 1 a and b represent the mean average deviation (mad) of the detected sine waves v a and v b . the polarity of v out is affected by the sign of the a comparator, i.e., multiply v out +1 for a comp+ > a compC , and v out C1 for a compC > a comp+ . 2 nonlinearity of the AD698 only in units of ppm of full scale. nonlinearity is defined as the maximum measured deviation of the AD698 output voltage from a straight line. the straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage. 3 see transfer function. 4 for example, if the excitation to the primary changes by 1 db, the gain of the system will change by typically 100 ppm. 5 output ripple is a function of the AD698 bandwidth determined by c1 and c2. a 1000 pf capacitor should be connected in parallel with r2 to reduce the output ripple. see figures 7, 8 and 13. 6 r1 is shown in figures 7, 8 and 13. 7 excitation voltage drift is not an important specification because of the ratiometric operation of the AD698. 8 from t min to t max the overall error due to the AD698 alone is determined by combining gain error, gain drift and offset drift. for example, the typical overall error for the AD698ap from t min to t max is calculated as follows: overall error = gain error at +25 c ( 0.2% full scale) + gain drift from C40 c to +25 c (20 ppm/ c 65 c) + offset drift from C40 c to +25 c (5 ppm/ c 65 c) = 0.36% of full scale. note that 1000 ppm of full scale equals 0.1% of full scale. specifications subject to change without notice. specifications shown in boldface are tested on all production units at final electrical test. results from those tested are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. ordering guide model package description package option AD698ap 28-pin plcc p-28a AD698sq 24-pin double cerdip q-24a connection diagrams 28-pin plcc 7 8 9 10 11 5 6 28 27 26 1 2 3 4 21 22 23 24 25 19 20 12 13 14 15 16 17 18 top view (not to scale) lev1 lev2 freq1 nc nc sig ref sig out feedback out filt nc = no connect AD698 bfilt1 bfilt2 afilt1 afilt2 +acomp freq2 nc exc2 exc1 ? s +v s nc ?in +bin ?in +ain ?comp off1 off2 24-pin cerdip 13 16 15 14 24 23 22 21 20 19 18 17 top view (not to scale) 12 11 10 9 8 1 2 3 4 7 6 5 AD698 ? s sig ref offset2 offset1 +v s exc1 exc2 lev1 out filt feedback sig out lev2 freq1 freq2 bfilt1 bfilt2 ?in ?comp afilt2 afilt1 +bin ?in +acomp +ain warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD698 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings total supply voltage (+v s to Cv s ) . . . . . . . . . . . . . . . . . 36 v storage temperature range p package . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c q package . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range AD698sq . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c AD698ap . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c power dissipation derates above +65 c p package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mw/ c q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mw/ c thermal characteristics q jc q ja p package 30 c/w 60 c/w q package 26 c/w 62 c/w
rev. b C4C AD698 typical characteristics (at +25 c and v s = 15 v unless otherwise noted) 240 ?0 140 20 0 ?0 ?0 80 40 120 160 200 120 100 80 60 40 20 0 ?0 temperature ? c gain and offset psrr ?ppm/v offset psrr 12?5v offset psrr 15?8v gain psrr 12?5v gain psrr 15?8v figure 1. gain and offset psrr vs. temperature 140 ?0 ?0 120 100 80 60 40 20 0 ?0 0 ?5 ?5 ?0 ?0 ?5 ?0 ?5 ?0 ?5 temperature ? c gain and offset cmrr ?ppm/v offset cmrr 3v gain cmrr 3v figure 2. gain and offset cmrr vs. temperature 120 ?0 140 ?0 ?0 ?0 ?0 0 ?0 20 40 80 120 100 80 60 40 20 0 ?0 temperature ? c typical gain drift ?ppm/ c figure 3. typical gain drift vs. temperature 20 ?0 140 ?0 ?5 ?0 ?0 0 ? 5 10 15 120 100 80 60 40 20 0 ?0 temperature ? c typical offset drift ?ppm/ c figure 4. typical offset drift vs. temperature
AD698 rev. b C5C theory of operation a block diagram of the AD698 along with an lvdt (linear variable differential transformer) connected to its input is shown in figure 5 below. the lvdt is an electromechanical trans- ducerits input is the mechanical displacement of a core, and its output is an ac voltage proportional to core position. two popular types of lvdts are the half-bridge type and the series opposed or four-wire lvdt. in both types the moveable core couples flux between the windings. the series-opposed con- nected lvdt transducer consists of a primary winding ener- gized by an external sine wave reference source and two second ary windings connected in the series opposed configuration. the output voltage across the series secondary increases as the core is moved from the center. the direction of movement is detected by measuring the phase of the output. half-bridge lvdts have a single coil with a center tap and work like an autotransformer. the excitation voltage is applied across the coil; the voltage at the center tap is proportional to position. the device behaves similarly to a resistive voltage divider. a b amp oscillator voltage reference a b filter amp AD698 figure 5. functional block diagram the AD698 energizes the lvdt coil, senses the lvdt output voltages and produces a dc output voltage proportional to core position. the AD698 has a sine wave oscillator and power am- plifier to drive the lvdt. two synchronous demodulation stages are available for decoding the primary and secondary voltages. a decoder determines the ratio of the output signal voltage to the input drive voltage (a/b). a filter stage and out- put amplifier are used to scale the resulting output. the oscillator comprises a multivibrator that produces a triwave output. the triwave drives a sine shaper that produces a low dis- tortion sine wave. frequency and amplitude are determined by a single resistor and capacitor. output frequency can range from 20 hz to 20 khz and amplitude from 2 v to 24 v rms. total har- monic distortion is typically C50 db. the AD698 decodes lvdts by synchronously demodulating the amplitude modulated input (secondaries), a, and a fixed in- put reference (primary or sum of secondaries or fixed input), b. a common problem with earlier solutions was that any drift in the amplitude of the drive oscillator corresponded directly to a gain error in the output. the AD698, eliminates these errors by calculating the ratio of the lvdt output to its input excitation in order to cancel out any drift effects. this device differs from the ad598 lvdt signal conditioner in that it implements a different circuit transfer function and does not require the sum of the lvdt secondaries (a + b) to be constant with stroke length. the AD698 block diagram is shown below. the inputs consist of two independent synchronous demodulation channels. the b channel is designed to monitor the drive excitation to the lvdt. the full wave rectified output is filtered by c2 and sent to the computational circuit. channel a is identical except that the comparator is pinned out separately. since the a channel may reach 0 v output at lvdt null, the a channel demodulator is usually triggered by the primary voltage (b channel). in addi- tion, a phase compensation network may be required to add a phase lead or lag to the a channel to compensate for the lvdt primary to secondary phase shift. for half-bridge circuits the phase shift is noncritical, and the a channel voltage is large enough to trigger the demodulator. AD698 comp 1 filter b channel ?in +bin duty cycle divider a/b = 1 = 100% duty 1 ?comp +acomp ?in +ain filter demodulator a channel a b off 2 off 1 bfilt1 bfilt2 c2 v out iref 500? v out filter c4 fb r2 c5 +v s ? s afilt2 afilt1 c3 v/i comp v/i figure 6. AD698 block diagram once both channels are demodulated and filtered a division cir- cuit, implemented with a duty cycle multiplier, is used to calcu- late the ratio a/b. the output of the divider is a duty cycle. when a/b is equal to 1, the duty cycle will be equal to 100%. (this signal can be used as is if a pulse width modulated output is required.) the duty cycle drives a circuit that modulates and filters a reference current proportional to the duty cycle. the output amplifier scales the 500 m a reference current converting it to a voltage. the output transfer function is thus: v out = i ref a / b r 2, where i ref = 500 m a
rev. b C6C AD698 connecting the AD698 the AD698 can easily be connected for dual or single supply operation as shown in figures 7, 8 and 13. the following gen- eral design procedures demonstrate how external component values are selected and can be used for any lvdt that meets AD698 input/output criteria. the connections for the a and b channels and the a channel comparators will depend on which transducer is used. in general follow the guidelines below. parameters set with external passive components include: exci- tation frequency and amplitude, AD698 input signal frequency, and the scale factor (v/inch). additionally, there are optional features; offset null adjustment, filtering, and signal integration, which can be implemented by adding external components. r1 c1 15nf c2 c3 r4 r3 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD698 ? s exc1 exc2 lev1 lev2 freq1 bfilt1 bfilt2 ?in +bin ?in freq2 sig ref offset2 offset1 +v s out filt feedback sig out ?comp afilt2 afilt1 +acomp +ain c4 r2 33k w 1000pf signal reference r l v out 100nf 6.8? ?5v +15v 100nf 6.8? figure 7. interconnection diagram for half-bridge lvdt and dual supply operation design procedure dual supply operation figure 7 shows the connection method for half-bridge lvdts. figure 8 demonstrates the connections for 3- and 4-wire lvdts connected in the series opposed configuration. both ex- amples use dual 15 volt power supplies. a. determine the oscillator frequency frequency is often determined by the required bw of the sys- tem. however, in some systems the frequency is set to match the lvdt zero phase frequency as recommended by the manufacturer; in this case skip to step 4. 1. determine the mechanical bandwidth required for lvdt position measurement subsystem, f subsystem . for this ex- ample, assume f subsystem = 250 hz. 2. select minimum lvdt excitation frequency approximately 10 f subsystem . therefore, let excitation frequency = 2.5 khz. 3. select a suitable lvdt that will operate with an excitation frequency of 2.5 khz. the schaevitz e100, for instance, will operate over a range of 50 hz to 10 khz and is an eligible candidate for this example. 4. select excitation frequency determining component c1. c 1 = 35 m fhz / f excitation r1 c1 c2 c3 r4 r3 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD698 ? s exc1 exc2 lev1 lev2 freq1 bfilt1 bfilt2 ?in +bin ?in freq2 sig ref offset2 offset1 +v s out filt feedback sig out ?comp afilt2 afilt1 +acomp +ain c4 r2 1000pf signal reference r l v out 100nf 6.8? ?5v +15v 100nf 6.8? 1m ab c d phase lag/lead network r t ab cd phase lead r s c c r s r s r t a b cd phase lag c phase lag = arc tan (hz rc); phase lead = arc tan 1/(hz rc) where r = r s // (r s + r t ) figure 8. AD698 interconnection diagram for series opposed lvdt and dual supply operation b. determine the oscillator amplitude amplitude is set such that the primary signal is in the 1.0 v to 3.5 v rms range and the secondary signal is in the 0.25 v to 3.5 v rms range when the lvdt is at its mechanical full-scale position. this optimizes linearity and minimizes noise suscepti- bility. since the part is ratiometric, the exact value of the excita- tion is relatively unimportant. 5. determine optimum lvdt excitation voltage, v exc . for a 4-wire lvdt determine the voltage transformation ratio, vtr, of the lvdt at its mechanical full scale. vtr = lvdt sensitivity maximum stroke length from null. lvdt sensitivity is listed in the lvdt manufacturers cata- log and has units of volts output per volts input per inch dis- placement. the e100 has a sensitivity of 2.4 mv/v/mil. in the event that lvdt sensitivity is not given by the manufac- turer, it can be computed. see section on determining lvdt sensitivity.
AD698 rev. b C7C b. full-scale core displacement from null, d s d = vtr and also equals the ratio a/b at mechanical full scale. the vtr should be converted to units of v/v. for a full-scale displacement of d inches, voltage out of the AD698 is computed as v out = s d 500 m a r 2 v out is measured with respect to the signal reference, pin 21, shown in figure 7. solving for r2, r 2 = v out s d 500 m a (1) for v out = 10 v full-scale range (20 v span) and d = 0.1 inch full-scale displacement (0.2 inch span) r 2 = 20 v 2. 4 0. 2 500 m a = 83. 3 k w v out as a function of displacement for the above example is shown in figure 10. +10 +0.1d (inches) ?.1 ?0 v out (volts) figure 10. v out ( 10 v full scale) vs. core displace- ment ( 0.1 inch) e. optional offset of output voltage swing 9. selections of r3 and r4 permit a positive or negative output voltage offset adjustment. v os = 1. 2 v r 2 1 r 3 + 2 k w 1 r 4 + 2 k w ? ? ? (2) for no offset adjustment r3 and r4 should be open circuit. to design a circuit producing a 0 v to +10 v output for a displacement of +0.1 inch, set v out to +10 v, d = 0.2 inch and solve equation (1) for r2. +5 +0.1d (inches) ?.1 ? v out (volts) figure 11. v out ( 5 v full scale) vs. core displacement ( 0.1 inch) this will produce a response shown in figure 11. in equation (2) set v os = 5 v and solve for r3 and r4. since a positive offset is desired, let r4 be open circuit. rearranging equation (2) and solving for r3 r 3 = 1. 2 r 2 v os 2 k w= 7. 02 k w multiply the primary excitation voltage by the vtr to get the expected secondary voltage at mechanical full scale. for example, for an lvdt with a sensitivity of 2.4 mv/v/mil and a full scale of 0.1 inch, the vtr = 0.0024 v/v/mil 100 mil = 0.24. assuming the maximum excitation of 3.5 v rms, the maximum secondary voltage will be 3.5 v rms 0.24 = 0.84 v rms, which is in the acceptable range. conversely the vtr may be measured explicitly. with the lvdt energized at its typical drive level v pri , as indicated by the manufacturer, set the core displacement to its me- chanical full-scale position and measure the output v sec of the secondary. compute the lvdt voltage transformation ratio, vtr. vtr = v sec //vpri. for the e100, v sec = 0.72 v for v pri = 3 v. vtr = 0.24. for situations where lvdt sensitivity is low, or the me- chanical fs is a small fraction of the total stroke length, an input excitation of more than 3.5 v rms may be needed. in this case a voltage divider network may be placed across the lvdt primary to provide smaller voltage for the +bin and Cbin input. if, for example, a network was added to divide the b channel input by 1/2, then the vtr should also be re- duced by 1/2 for the purpose of component selection. check the power supply voltages by verifying that the peak values of v a and v b are at least 2.5 volts less than the volt- ages at +v s and Cv s . 6. referring to figure 9, for v s = 15 v, select the value of the amplitude determining component r1 as shown by the curve in figure 9. 30 15 0 0.01 0.1 1k 10 0 10 1 5 10 20 25 v rms r1 k w v exc ?v rms figure 9. excitation voltage v exc vs. r1 7. c2, c3 and c4 are a function of the desired bandwidth of the AD698 position measurement subsystem. they should be nominally equal values. c 2 = c 3 = c 4 = 10 C4 farad hz/f 5ubsystem ( hz ) if the desired system bandwidth is 250 hz, then c 2 = c 3 = c 4 = 10 -4 f arad hz /250 hz = 0.4 m f see figures 14, 15 and 16 for more information about AD698 bandwidth and phase characterization. d. set the full-scale output voltage 8. to compute r2, which sets the AD698 gain or full-scale output range, several pieces of information are needed: a. lvdt sensitivity, s
rev. b C8C AD698 note that v os should be chosen so that r3 cannot have negative value . figure 12 shows the desired response. +5 +0.1d (inches) ?.1 v out (volts) +10 figure 12. v out (0 vC10 v full scale) vs. displacement ( 0.1 inch) design procedure single supply operation figure 13 shows the single supply connection method. r1 c1 c2 c3 r4 r3 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD698 ? s exc1 exc2 lev1 lev2 freq1 bfilt1 bfilt2 ?in +bin ?in freq2 sig ref offset2 offset1 +v s out filt feedback sig out ?comp afilt2 afilt1 +acomp +ain c4 r2 1000pf signal reference r l v out 0.1? v ps +30v 6.8? 1m r6 r5 c5 ab c d phase lag/lead network r t ab cd phase lead r s c c r s r s r t a b cd phase lag c phase lag = arc tan (hz rc); phase lead = arc tan 1/(hz rc) where r = r s // (r s + r t ) figure 13. interconnection diagram for single supply operation for single supply operation, repeat steps 1 through 10 of the design procedure for dual supply operation. r5, r6 and c5 are additional component values to be determined. v out is mea- sured with respect to signal reference. 10. compute a maximum value of r5 and r6 based upon the relationship r 5 + r 6 v ps /100 m a 11. the voltage drop across r5 must be greater than 2 + 10 k w 1. 2 v r 4 + 2 k w + 250 m a + v out 4 r 2 ? ? ? volts therefore r 5 3 2 + 10 k w 1. 2 v r 4 + 2 k w + 250 m a + v out 4 r 2 ? ? ? 100 m a ohms based upon the constraints of r5 + r6 (step 10) and r5 (step 11), select an interim value of r6. 12. load current through r l returns to the junction of r5 and r6, and flows back to v ps . under maximum load condi- tions, make sure the voltage drop across r5 is met as de- fined in step 11. as a final check on the power supply voltages, verify that the peak values of v a and v b are at least 2.5 volts less than the voltage between +v s and Cv s . 13. c5 is a bypass capacitor in the range of 0.1 m f to 1 m f. gain phase characteristics to use an lvdt in a closed-loop mechanical servo application, it is necessary to know the dynamic characteristics of the trans- ducer and interface elements. the transducer itself is very quick to respond once the core is moved. the dynamics arise prima- rily from the interface electronics. figures 14, 15 and 16 show the frequency response of the AD698 lvdt signal condi tioner. note that figures 15 and 16 are basically the same; the differ- ence is frequency range covered. figure 15 shows a wider range of mechanical input frequencies at the expense of accuracy. frequency ?hz 0 10k 100 1k 10 0 ?0 ?0 ?0 0 ?0 ?0 ?0 ?0 gain ?db ?60 ?0 ?40 ?00 ?20 ?80 ?20 phase shift ?degrees 0.1? 0.33? 2.0? r2 = 81k w f exc = 2.5khz 0.1? 0.33? 2.0? r2 = 81k w f exc = 2.5khz figure 14. gain and phase characteristics vs. frequency (0 khzC10 khz)
AD698 rev. b C9C frequency ?hz 0 100k 100 1k 10k 10 0 ?0 ?0 ?0 0 ?0 ?0 ?0 ?0 ?60 ?0 ?40 ?00 ?20 ?80 ?20 gain ?db phase shift ?degrees 0.1? 0.033? 0.01? r2 = 81k w f exc = 10khz 0.1? 0.033? 0.01? r2 = 81k w f exc = 10khz figure 15. gain and phase characteristics vs. frequency (0 khzC50 khz) frequency ?hz 0 100 1k 10k 10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?60 ?0 ?40 ?00 ?80 ?20 gain ?db phase shift ?degrees 0.1? 0.033? 0.01? r2 = 81k w f exc = 10khz 0.1? 0.033? 0.01? r2 = 81k w f exc = 10khz figure 16. gain and phase characteristics vs. frequency (0 khzC10 khz) figure 16 shows a more limited frequency range with enhanced accuracy. the figures are transfer functions with the input to be considered as a sinusoidally varying mechanical position and the output as the voltage from the AD698; the units of the transfer function are volts per inch. the value of c2, c3, and c4, from figure 7, are all equal and designated as a parameter in the fig- ures. the response is approximately that of two real poles. however, there is appreciable excess phase at higher frequen- cies. an additional pole of filtering can be introduced with a shunt capacitor across r2, figure 7; this will also increase phase lag. when selecting values of c2, c3 and c4 to set the bandwidth of the system, a trade-off is involved. there is ripple on the dc position output voltage, and the magnitude is determined by the filter capacitors. generally, smaller capacitors will give higher system bandwidth and larger ripple. figures 17 and 18 show the magnitude of ripple as a function of c2, c3 and c4, again all equal in value. note also a shunt capacitor across r2, figure 7, is shown as a parameter. the value of r2 used was 81 k w with a schaevitz e100 lvdt. c2, c3, c4; c2 = c3 = c4 ? m f ripple ?mv rms 1k 100 0.1 0.01 0.1 10 1 10 1 2.5khz, c shunt 1nf 2.5khz, c shunt 10nf figure 17. output voltage ripple vs. filter capacitance c2, c3, c4; c2 = c3 = c4 ? m f ripple ?mv rms 1k 100 0.1 0.001 0.01 10 0.1 10 1 10khz, c shunt 1nf 10khz, c shunt 10nf 1 figure 18. output voltage ripple vs. filter capacitance
rev. b C10C AD698 determining lvdt sensitivity lvdt sensitivity can be determined by measuring the lvdt secondary voltages as a function of primary drive and core posi- tion, and performing a simple computation. energize the lvdt at its recommended primary drive level, v pri (3 v rms for the e100). set the core displacement to its mechanical full-scale position and measure secondary voltages v a and v b . sensitivity = v secondary v pri d from figure 19, sensitivity = 0. 72 3 v 100 mils = 2. 4 mv / v mil d = ?00 mils d = 0 1.71v rms 0.99v rms d = +100 mils v sec when v pri 3v rms v a v b figure 19. lvdt secondary voltage vs. core displacement thermal shutdown and loading considerations the AD698 is protected by a thermal overload circuit. if the die temperature reaches 165 c, the sine wave excitation amplitude gradually reduces, thereby lowering the internal power dissipa- tion and temperature. due to the ratiometric operation of the decoder circuit, only small errors result from the reduction of the excitation ampli- tude. under these conditions the signal-processing section of the AD698 continues to meet its output specifications. the thermal load depends upon the voltage and current deliv- ered to the load as well as the power supply potentials. an lvdt primary will present an inductive load to the sine wave excitation. the phase angle between the excitation voltage and current must also be considered, further complicating thermal calculations. applications most of the applications for the ad598 can also be imple- mented with the AD698. please refer to the applications written for the ad598 for a detailed explanation. see ad598 data sheet for: C proving ring-weigh scale C synchronous operation of multiple lvdts C high resolution position-to-frequency circuit C low cost setpoint controller C mechanical follower servo loop C differential gaging and precision differential gaging ac bridge signal conditioner bridge circuits which use dc excitation are often plagued by er- rors caused by thermocouple effects, 1/f noise, dc drifts in the electronics, and line noise pickup. one way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously de- modulate the resulting signal. the ac phase and amplitude in- formation from the bridge is recovered as a dc signal at the output of the synchronous demodulator. the low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a low- pass filter. the AD698 with the addition of a simple ac gain stage can be used to implement an ac bridge. figure 20 shows the connec- tions for such a system. the AD698 oscillator provides ac excitation for the bridge. the low level bridge signal is amplified by the gain stage created by a1, a2 to provide a differential in- put to the a channel of the AD698. the signal is then synchro- nously detected by a channel. the b channel is used to detect the level of the bridge excitation. the ratio of a/b is then calcu- lated and converted to an output voltage by r2. an optional phase lag/lead network can be added in front of the a compara- tor to adjust for phase delays through the bridge and the ampli- fier, or if the phase delay is small, it can be ignored or compensated for by a gain adjustment. this circuit can be used for resistive bridges such as strain gages, or for inductive or capacitive bridges that are commonly used for pressure or flow sensors. the low level signal outputs of these sensors are susceptible to noise and interference and are good candidates for ac signal processing techniques. component selection amplifiers a1, a2 will be chosen depending on the type of bridge that is conditioned. capacitive bridges should use an amplifier with low bias current; a large bleeder resistor will be required from the amplifier inputs to ground to provide a path for the dc bias current. resistive and inductive bridges can use a more general purpose amplifier. the dc performance of a1, a2 are not as important as their ac performance. dc errors such as voltage offset will be chopped out by the AD698 since they are not synchronous to the carrier frequency. the oscillator amplitude and span resistor for the AD698 may be chosen by first computing the transfer function or sensitivity of the bridge and the ac amplifier. this ratio will correspond to the a/b term in the AD698 transfer function. for example, sup- pose that a resistive strain gage with a sensitivity, s, of 2 mv/v at full scale is used. select an arbitrary target value for a/b that is close to its maximum value such as a/b = 0.8. then choose a gain for the ac amplifier so that the strain gage transfer function from excitation to output also equals 0.8. thus the required am- plifier gain will be [a/b]/ s; or 0.8/ 0.002 v/v = 400. then select values for r s and r g . for the gain stage:
AD698 rev. b C11C v out = 2 r s r g + 1 ? ? v in solving for v out /v in = 400 and setting r g = 100 w then: r s = [400 C 1] r g /2 = 19.95 k w choose an oscillator amplitude that is in the range of 1 v to 3.5 v rms. for an input excitation level of 3 v rms, the output signal from the amplifier gain stage will be 3.5 v rms 0.8 v or 2.4 v rms, which is in the acceptable range. since a/b is known, the value of r2, the output fs resistor may be chosen by the formula: v out = a / b 500 m a r 2 for a 10 v output at fs, with an a/b of 0.8; solve for r2. r 2 = 10 v [0.8 500 m a] = 25.0 k w this will result in a v out of 10 v for a full-scale signal from the bridge. the other components, c1, c2, c3, c4 may be selected by following the guidelines on general device operation men- tioned earlier. if a gain trim is required, then a trim resistor can be used to ad- just either r2 or r g . bridge offsets should be adjusted by a trim network on the offset 1 and offset 2 pins of the AD698. r1 c1 c2 c3 r4 r3 c4 r2 1000pf signal reference r l v out 100nf 6.8? ?5v +15v 100nf 6.8? ab c d phase lag/lead network 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD698 ? s exc1 exc2 lev1 lev2 freq1 bfilt1 bfilt2 ?in +bin ?in freq2 sig ref offset2 offset1 +v s out filt feedback sig out ?comp afilt2 afilt1 +acomp +ain a2 r s a1 r s resistors, inductors or capacitors r t ab cd phase lead r s c c r s r s r t a b cd phase lag c phase lag = arc tan (hz rc); phase lead = arc tan 1/(hz rc) where r = r s // (r s + r t ) r g dual op amp figure 20. AD698 interconnection diagram for ac bridge applications
rev. b C12C AD698 outline dimensions dimensions shown in inches and (mm). 24-pin cerdip (wide) 0.620 (15.75) 0.590 (15.00) 0.015 (0.38) 0.008 (0.20) 15 0 1.280 (32.51) max 0.200 (5.08) max 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min seating plane 0.005 (0.13) min pin 1 1 24 0.098 (2.49) max 0.610 (15.5) 0.520 (13.2) 12 13 28-pin plcc 0.048 (1.21) 0.042 (1.07) 0.456 (11.58) 0.450 (11.43) sq 0.495 (12.57) 0.485 (12.32) sq 0.048 (1.21) 0.042 (1.07) 0.050 (1.27) bsc 26 4 top view 25 19 12 11 pin 1 identifier 5 18 0.020 (0.50) r 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.180 (4.57) 0.165 (4.19) 0.430 (10.92) 0.390 (9.91) 0.110 (2.79) 0.085 (2.16) 0.040 (1.01) 0.025 (0.64) c1827aC5C7/95 printed in u.s.a.

▲Up To Search▲

Price & Availability of AD698

	To Download AD698 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .